1. Field of the Invention
The present invention relates to a semiconductor integrated logic circuit, and more specifically to a semiconductor logic integrated circuit having a scan path testing function.
2. Description of Related Art
In the prior art, in the case of testing a semiconductor logic integrated circuit, a so called scan path test method has been used in order to realize controllability of the circuit and to improve observability.
However, this scan path test method is not perfect. When an integrated circuit includes a large-scaled macrocell such as a memory circuit (RAM, etc.), it is difficult to test all of the integrated circuit by the scan path test method. In this case, the scan path test method and another test method must be used in combination.
FIG. 1 is a block diagram of the semiconductor logic integrated circuit for illustrating one prior art example. As shown in FIG. 1, a prior art semiconductor logic integrated circuit 1a including a large-scaled macrocell 2 includes flipflop circuits (called "F/F circuit" hereinafter) 4A and 4D enabling a scan path test. In the scan path testing, these F/F circuits 4A and 4D are connected in cascade between a scan path test input terminal SCAN.cndot.IN and a scan path test output terminal SCAN.cndot.OUT, in order to test an internal circuit, etc. In this case, the internal cascaded F/F circuits 4A and 4D are set to arbitrary values through the input terminal SCAN.cndot.IN directly from an external, and the value of the F/F circuits 4A and 4D are read out directly to the output terminal SCAN.cndot.OUT.
In addition, the semiconductor logic integrated circuit 1a includes a built-in self test circuit (called a "BIST circuit" hereinafter) 16 for automatically generating a test pattern when the large-scaled macrocell 2 is tested. In this case, a control signal and a clock are supplied from a macrocell test input to the BIST circuit 16, and further, a latch-off signal is supplied from the macrocell test input. This latch-off signal is a signal. for turning off input latch circuits 14 and output latch circuits 15 which are used when a normal data input/output is carried out for the macrocell 2. On the basis of the control signal from the test input, the BIST circuit 16 accesses the macrocell 2, and outputs a signal indicative of whether or not a read-out data is normal, to a macrocell test output. The testing of the macrocell 2 is conducted by checking, outside of the integrated circuit, the signal indicative of whether or not the read-out data is normal. Incidentally, in the course of the macrocell testing, the input and output latch circuits 14 and 15 are maintained off in order to prevent an input/output of another data.
As mentioned above, at the time of testing the prior art semiconductor logic integrated circuit 1a, it is necessary to use the scanpath-testable F/F circuits 4A and 4D for testing an ordinary internal circuit, and on the other hand, when the integrated circuit includes the memory circuit such as the RAM, as the macrocell 2, it is necessary to previously provide for example the BIST circuit 16 internally in the integrated circuit.
When the semiconductor logic integrated circuit adopting the above mentioned prior art scan path test method includes the large-scaled macrocell, since the macrocell is large in scale, a different testing method must be used in testing the macrocell. In this case, accordingly, another testing terminal is disadvantageously required in addition to the test terminals required for the scan path test method.
In addition, in the prior art semiconductor logic integrated circuit, whether or not the logic condition of a first stage of the input latch circuits and a final stage of the output latch circuit is normal, cannot disadvantageously be ascertained by either the scan path testing or the testing of the macrocell.
Furthermore, in the prior art semiconductor logic integrated circuit, since a test pattern required for the scan path test and a different test pattern for the macrocell test, etc. are separately used, a test time disadvantageously becomes long.